The present invention relates to chip area reduction techniques for semiconductor devices, and more particularly to a technique useful for layout area reduction in the “PAD on I/O (Input/Output)” cell structure.
In recent years, with the growing demand for low-cost and smaller semiconductor integrated circuit devices, efforts towards cost reduction with smaller semiconductor chip sizes have been made. For smaller chip sizes, it is necessary to reduce the layout area in which components to be packaged are arranged.
One of the known layout area reduction techniques is that pads coupled with bonding wires or the like are overlapped with I/O cells as interfaces with the outside, which is called the “PAD on I/O cell” structure.